PMC-ATM

Features

155Mbps ATM Network Interface
Validated with VxWorks and Linux
Fully supports CBR and UBR service classes, VBR and ABR upon request
Validated with popular TCP/IP protocols such as Classical-IP (CLIP) and ATM Forum LANE
Embedded software includes user accessible high coverage built in test (BIT)
Extensively tested in extreme environments
Available as air cooled commercial product or militarized conduction cooled

The PMC-ATM OC-3 NIC is a high performance ATM network interface ideally suited for replacing aging technology products as well as providing a migration path to more contemporary interfaces such as Gigabit Ethernet. The design is implemented using a combination of a general purpose communications processor coupled with a high density CPLD. This combination enables the board to be register level compatible with legacy Integrated Device Technology IDT77211A hardware thus enabling operation with existing drivers and applications.

The PMC-ATM interfaces to the system at the PCI register level. The software interface closely reproduces that of the IDT77211A Nicstar™. The PMC-ATM architecture buffers Convergence Sub-layer Protocol Data Units (CS-PDU) in host memory rather than in on-board. It uses the PCI bus master capability to access the host memory to reduce host CPU utilization copying data. The PMC-ATM processor controls all AAL SAR and ATM layer run-time operations and performs all key data transfers between the host system and itself as a PCI bus master. The host device driver provides the PMC-ATM with buffer and control descriptors during run-time. When receiving cells, the PMC-ATM performs a table lookup using the connection number, in the cell header, to determine where to place the cell payload in the host memory. The ATM cell payloads received from the network are then placed directly into host memory to form CS-PDUs. When transmitting cells the CS-PDUs are queued in host memory by the host driver software. As the PMC-ATM segments CS-PDU buffers into ATM cell payloads, it appends the respective cell headers to create 53-byte ATM cells. The Header Error Check (HEC) byte is inserted as a place holder by the PMC-ATM. The cells are then transmitted to the PHY device as allocated by a scheduling table. The PHY device then calculates and replaces the HEC byte to form the complete 53-byte ATM cell.

The PMC-ATM also features a separate built in test interface that is implemented through an extension of the command set to the board as well as the inclusion of a separate PCI register to report results. The built in test module can be run at power on to guarantee the board is fully functional. Test coverage is very high and includes the ability to test all major data paths, actual data transmission and reception, bit error rates and data transfer rates.

Extensive software compatibility testing has been done with Linux and VxWorks. The testing included both unit level tests as well as system level tests featuring many different packet sizes, transmission rates, data formats, etc. Similarly the hardware has been validated with a significant number of foreign devices such as ATM switches and other types of ATM NICs.

PCI INTERFACE

32 Bit / 33 Mhz
5V and 3.3V compatible

COMMUNICATIONS PROCESSOR

Freescale MPC8358 @ 400 MHz
RISC Co-Processor
Multi-channel DMA Engine

DDR2 SDRAM

64 Mbytes @ 266 MHz Operation

FLASH EEPROM

512 Mbits NOR, 16 bit bus interface

ATM PHY

Processes duplex bit-serial 155.52 Mbit/s data streams
Complies with Bellcore GR-253-CORE (2000 Issue) jitter tolerance, jitter transfer (1995 issue), and intrinsic jitter

ETHERNET PHY

Marvell 88E111

MECHANICAL AND ENVIRONMENTAL DATA

Single PMC form-factor: Conduction or Convection Cooled
Operating Temperature: -40 to +85C
Storage Temperature: -55 to +100C
Shock: 40G ½ sine, 20 mS
Random Vibration: 0.1g2/Hz 5-1000Hz
Sine Vibration: 5g 32-2000Hz
Humidity: Commercial 95% non-condensing
Reliability data: 217-F, GB, 25C estimated to exceed 350,000 hours